In addition to maintaining 8086/80386 80386 related functions, but also enhanced interrupt handling capability, and the concept of "exception" concept. This article will introduce the 80386 interrupt and exception mechanism. Download the article all the source code.
8086/8088 to break into the internal interrupt and external interrupt two categories. In order to support multi-tasking and virtual memory and other functions, 80,386 external interrupt known as the "break", the internal interrupt as "abnormal." As with the 8086/8088, 80386 usually between the two commands to respond to interrupt or exception. 80386 handle up to 256 interrupt or exception.
1. Interrupted
On the 80386, the interrupt is caused by asynchronous external events. External events and interrupt response and is not related to the implementation of the directive. Typically, the interrupt to indicate I / O device has completed an operation. As with the 8086/8088, 80386 INTR and NMI are two pins accept external interrupt request signal. INTR accepted maskable interrupt request. NMI received interrupt request can not be shielded. In 80386, the flag register IF flag in EFLAGS to decide whether screening can shield interrupt request.
External hardware through an interrupt request signal INTR the same time, but also to give an 8-bit processor interrupt vector. Processor in response to maskable interrupt request, read the paper by the external hardware interrupt vector number. Processor interrupt vector of this number and does not provide. But in the specific computer system, the system must meet the set of software and hardware, so given the interrupt vector number corresponds not only with the external interrupt sources and interrupt vector number used to avoid the appearance of conflict. 8259A programmable interrupt controller chip can work with the 80386, can be set to the processor according to the interrupt vector number, can handle the priority interrupt request. Each 8259A chip can support 8 interrupt request signal, if you use 9 8259A chip (a master piece, eight from the film), would enable a single pin INTR 80386 accepted up to 64 interrupt sources, interrupt request signal .
Processor does not mask the interrupt request from the NMI. Processor in response to NMI interrupt is not received from the external hardware interrupt vector number. And 8086/8088, as in 80386, the non-maskable interrupt the corresponding interrupt vector number is fixed at 2. For non-maskable interrupt nesting, when receiving an NMI interrupt, the processor again in response to the internal shielding of the NMI, the implementation of the screening process until after the end of the interrupt return instruction IRET. Therefore, NMI handler should be the end of IRET instruction.
2. Exception
80386 instruction exception is detected during the implementation of irregular or illegal conditions are present. Abnormality in the execution of the instructions have a direct link. For example, the implementation of the divide instruction, the divisor is equal to 0. Again, the implementation of instruction privilege level is not correct when found. When these situations occur, the directive can not be completed successfully. Software interrupt instruction "INT n" and "INTO" also classified as abnormal and not interrupt, because the implementation of these instructions produced anomalies.
80386 identify different types of anomalies, and to give each category a different interrupt vector number. After the exception occurs, the processor so as to respond to interrupt handling exceptions. That under the interrupt vector number, switch to the corresponding interrupt handler. This interrupt handler is called the exception handler may be more appropriate.
Abnormal according to whether the procedure caused the restoration and recovery point can be different, to be further classified as abnormal fault (Fault), trap (Trap) and suspension (Abort). We were the corresponding exception handler is called fault handler, trap handlers and termination handlers.
Failure is caused by abnormalities in the instruction before it is notified to the system anomaly an exception. That the fault is 80386 can be excluded. When control is transferred to the fault handler, the saved CS and EIP values break point to lead to failure of the command. Thus, the fault handler to troubleshooting, the implementation of the IRET to return to the program caused by failure to execute, just lead to failure of command can be re-implemented. This re-run, no additional operating system software to participate. Failure of the findings may begin before the command may also be in the instruction execution period. If failures are detected during instruction execution, then the suspension of fault instruction, and instruction operands to restore the value before the instruction started. This will ensure the re-implementation of fault instruction to get the right results. For example, during the execution of an instruction, if we find there is no section, then stop the implementation of the directive, and notify the system to produce Fault, the corresponding segment fault handler can load the troubleshooting section of way, after which the original instruction can be successfully implemented, at least not non-existent fault segment occurred.
Trap is caused by abnormalities in the following instructions to inform the anomalies An exception to the system. When control is transferred to the exception handler, the saved CS and EIP break point to lead to trap the value of the next instruction to execute instructions. The next instruction to be executed, not necessarily the next instruction. Therefore, the trap handler does not always save the breakpoints according to the anti-push identify an exception instruction. When the trap handler in turn, lead to the completion of trap instruction to be normal, it is possible to change a register or memory cell. Software interrupt instruction, single-step exception is the example of the trap.
Suspension is a serious situation in the system, an exception notification system. Caused by the suspension order can not be determined. Produce termination, is the implementation of the program can not be reinstated. System receives the suspension, the processing procedure to re-establish the system forms, and may restart the operating system. Hardware failures and system tables in the illegal value or inconsistent value is suspended example.
3. Priority
In an instruction execution period into more than one interrupt is detected, or abnormal, then press the priorities listed in the table notification system. The highest priority interrupt or exception notification system, other lower-priority exception being abandoned, while the higher-priority interrupt will remain hanging.
80386 responses
Interrupt / exception priority interrupt / exception types the highest priority fault other fault 鈫?debug trap instruction INT n and INTO 鈫?鈫?NMI debug trap minimum disruption 鈫?INTR interrupt
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